The present invention relates to shift register circuits, and more particularly to shift register designs adapted for providing the lowest possible power consumption.
FIG. 1 illustrates one conventional design for a single stage static shift register. As with any shift register, this circuit 10 has a signal input in, a clock input ck and in this configuration complimentary outputs out and out*. The circuit is powered by a supply voltage provided by two rail voltages VDD and VSS.
This specific circuit uses an input signal buffer transistor MP1 that feeds a pair of cross-coupled transistors MP2 and MP3 to store the input signal state. Inverters INV1 and INV2 connected to the output of MP1 serve to buffer output voltage and current levels. Clock switch transistors MN1, MN2, MN3 and MN4 turn on the shift register to accept a digital input signal, such as from a previous stage.
The switches MN1-MN4 must be fully turned on or off for the shift register to function, thus requiring a full rail-to-rail voltage swing on their gate terminals. Even if external low voltage clock signals are applied, level shifters and clock buffers (not shown in FIG. 1) must be used to bring the gate control voltages to full rail voltage swing. Unfortunately, the power consumption in these clock buffers is equal to V2Cpfc, where V is the power supply voltage difference (VDD-VSS), Cp is the total parasitic capacitance connected to the clock buffer outputs, and fc is clock frequency. With a high voltage supply (10v or more), a large number of shift registers in series, long connection wires, and high clock frequency, a shift register using the stage circuit of FIG. 1 can therefore consume a significant amount of power.
FIG. 2 illustrates another known shift register stage circuit 20 that improves to some extent on the design of FIG. 1. This shift register stage circuit is adapted to operate with a low voltage swing clock signal, but high voltage swing logic circuits. For example, the voltage range between VDD and VSS might be 10 volts to provide high speed. However, the voltage swing from the clock input ck might be much less that—on the order of three volts or so—to reduce power consumption.
The input and output signals for the circuit 20 of FIG. 2 are as follows:    ck clock signal with peak-to-peak voltage from VEE to VDD (VEE>VSS)    e* complementary output from previous shift register stage    o and o* register output and its complementary output, respectively    r reset signal for individual shifter register    vgp an analog bias voltage    pc a pre-charge signal to initialize all shifter registers to low before start
The circuit 20 is configured such that an internal node a serves as both a collection point for input signal state and for driving output buffer INV1. Here, the number of state transistors has been reduced to only two, MP2 and MP1, arranged in cascode series. The ck signal input is fed to the source of MP2. The VDD supply voltage is fed to bias the body of transistor MP2. The gate of MP2 is fed by complimentary output from the previous shift register stage.
The gate of MP1 is controlled by vgp which is an analog bias voltage. MP1 is biased such that it conducts when its source voltage is greater than vgp by an amount, Vtp, where Vtp is the threshold voltage of MP1. A pre-charge input pc and a reset input r feed the drain of MP1 which also sets the voltage at node a.
In operation, the voltage vgp is thus set so that VEE-vgp<Vtp where Vtp is the threshold voltage of transistor MP1. When ck is low (VEE), MP1 is off and node a is held at its previous value; when ck is high (VDD) and the previous stage output e is high—which means that e* is low (VSS)—node a is charged up to a high voltage (VDD) through transistor MP1 and MP2.
The circuit 20 of FIG. 2 thus offers reduced power consumption as compared to the circuit 10 of FIG. 1. In designs such as this, however, with a high voltage swing shift register driven by a low voltage swing input clock, internal or external level shifters and clock buffers are thus often necessary.